The problem with silicon's thermo-optic coefficient
Silicon has a thermo-optic coefficient (dn/dT) of approximately 1.8 x 10-4 K-1 at 1310 nm. This means that for every degree Celsius the chip warms, the refractive index of silicon changes by about 0.018 percent. That sounds small. The problem is that photonic inference depends on precise phase relationships between optical paths, and those phase relationships are exquisitely sensitive to refractive index.
Consider a Mach-Zehnder interferometer with arms of length 500 micrometers. A 1 K temperature change produces a phase shift of roughly 2*pi*(dn/dT)*deltaT*L/lambda, which for these parameters works out to about 0.43 radians. For an MZI programmed to implement a specific weight value, that is a substantial unintended phase change that directly corrupts the encoded weight. In an N-by-N mesh with hundreds or thousands of MZI elements, uncorrected thermal drift destroys the accuracy of the computation within seconds of an initial calibration.
This is the central thermal engineering challenge in a photonic co-processor: the chip needs to either maintain a uniform, stable temperature across the entire waveguide mesh, or it needs active on-chip compensation that continuously corrects phase errors caused by temperature gradients.
Three thermal compensation strategies
The first approach is global temperature stabilization: run a thermoelectric cooler (TEC) under the chip to hold the die at a fixed temperature, independent of ambient and self-heating. This is the most straightforward approach from a signal-integrity standpoint. The drawback is power: a TEC consumes power proportional to the heat it needs to pump, and in a co-processor card sitting in a server rack with an ambient temperature that fluctuates between 20 and 40 degrees Celsius, the TEC power budget can be substantial. For an evaluation kit in a controlled lab environment, this is acceptable. For a production data-center card, the TEC power overhead must be included in the energy-per-token accounting, and it reduces the net energy advantage.
The second approach is differential MZI design: construct each MZI with matched arm lengths and route both arms through the same thermal environment, so that temperature changes affect both arms equally, canceling the phase drift. This works for slowly varying uniform temperature changes across the chip. It does not work for thermal gradients within the chip, which are common when some parts of the die (near the laser or the high-speed modulators) run hotter than others.
The third approach is active per-MZI feedback: integrate a temperature sensor (typically a p-n junction thermometer) near each MZI, and actively correct the phase setting of each MZI to compensate for the measured local temperature. This is architecturally the most robust approach and does not require global temperature control. The cost is circuit complexity: each MZI needs an associated feedback DAC, sensor readout, and control loop, which adds considerable chip area and digital control overhead.
Power budget implications of thermal compensation
Whatever thermal compensation strategy you choose, the power consumed by that compensation shows up in your total chip power draw. It is not free, and it must be included in any honest energy-per-MAC or energy-per-token comparison with digital hardware.
For global TEC stabilization, the TEC power draw in a data-center environment with 25-35 degree ambient temperatures and typical server airflow adds somewhere in the range of 5 to 20 watts per chip, depending on chip self-heating and thermal resistance of the packaging. For a chip drawing 10 to 15 watts for actual computation (laser, modulators, photodetectors, control electronics), a 10-watt TEC overhead is a significant fraction of the total power budget.
For active per-MZI feedback without a TEC, the compensation power comes primarily from the thermal phase shifters themselves. Correcting for a 1 K drift across an arm requires adjusting the phase shifter drive voltage. Silicon thermal phase shifters based on resistive heaters typically consume on the order of 10 to 50 milliwatts each to shift by pi radians. For a mesh with hundreds of MZIs, the aggregate correction power can reach several watts for large temperature excursions. This is manageable but not negligible.
Gradient management across the chip floorplan
Even with global temperature control, self-heating creates gradients. The modulator bank at the input of the chip generates heat from resistive driving of the phase shifters. The laser (if on-chip) or coupling region generates heat near the input edge. The photodetector array and TIA circuits generate heat at the output edge. The waveguide mesh in the center of the chip receives less direct self-heating but is affected by conduction from the hot edges.
In our chip floorplan work, we spend significant effort on thermal layout: distributing the high-power elements around the perimeter, placing thermal vias to spread heat into the package substrate, and deliberately sizing the mesh routing to maintain symmetric thermal environments for matched MZI pairs. Thermal simulation at the floor-planning stage (using tools that couple optical mode calculation with FEM thermal simulation) is an essential design step that academic photonic computing papers often omit because it is engineering work rather than physics work.
The gradient challenge worsens at scale. A larger chip with a bigger matrix mesh has a larger distance from center to edge, which means more thermal gradient for the same surface cooling. This is one reason why multi-chip architectures using smaller, well-thermally-controlled tiles may have advantages over single large chips at scale, beyond the coherence-length argument we discussed in an earlier post.
What this means for the data-center operating environment
Data-center servers run in environments with forced-air cooling, ambient temperatures up to 35 degrees Celsius at the server inlet, and airflow that varies with rack utilization. Photonic co-processor cards must be designed to maintain inference accuracy across this full operating range without relying on lab-grade temperature control infrastructure that is not present in production server rooms.
This is a harder engineering problem than it might appear in a lab setting. In our Boulder lab, we run our evaluation chips in a temperature-controlled enclosure with active TEC. That gives clean measurement data. The production path requires that we either tighten the passive thermal design to the point where ambient variation has acceptable impact, or implement robust active per-element feedback that does not depend on the server environment being special.
We are not at the point where we would describe this as a solved problem for production data-center deployment. It is an active engineering focus for us, and it is the kind of challenge that separates lab demonstrations of photonic computing from real production hardware. Anyone evaluating photonic inference hardware should ask for thermal sensitivity characterization data across the full operating temperature range, not just room-temperature benchmarks. We plan to provide exactly that for our evaluation kit program, because we think transparency about this challenge is more useful to the field than hiding it.