Why loss is the central engineering variable in photonic inference
In a digital processor, power consumption and thermal management are the dominant engineering constraints. In a photonic inference chip, optical loss occupies an analogous role: it determines how much signal reaches the detectors, which determines the signal-to-noise ratio of each multiply-accumulate output, which ultimately sets the precision of the inference result. Managing loss is not a secondary concern to be addressed after the architecture is fixed. It is a primary architectural constraint that should drive every design decision from day one.
This post walks through the main loss mechanisms in a silicon photonic inference chip, ordered roughly by where they appear in the signal path, and describes our thinking on minimizing each one.
Fiber-to-chip coupling loss
Before any optical computation happens, light must enter the chip from an external source. The standard approaches are grating couplers and edge couplers. Grating couplers are popular in research because they allow measurement from the top surface of the chip without polishing the facet. Typical coupling efficiency for a standard grating coupler in a 220 nm SOI process is around 2 to 4 dB per interface, and the coupling is strongly wavelength-dependent and sensitive to the polarization of the input fiber.
Edge couplers with inverse tapers can achieve lower coupling loss, typically 0.5 to 1.5 dB per facet, and are less polarization-sensitive. The trade-off is that edge coupling requires polished or cleaved chip facets and mechanical alignment in three dimensions with sub-micron tolerance. This is manageable in production packaging but is significantly more complex than grating coupler test setups.
For the GSK-1 architecture, we are targeting edge-coupled interfaces in the packaged product because the reduced coupling loss has a direct effect on the entire downstream signal budget. A 2 dB improvement at the input coupler is 2 dB that does not need to be recovered elsewhere.
Propagation loss in single-mode waveguides
Once light is on-chip, it travels through single-mode silicon waveguides. Propagation loss in these guides arises primarily from two sources: sidewall roughness scattering and absorption.
Sidewall roughness scattering is caused by the etching process that defines the waveguide geometry. Deep UV lithography and reactive ion etching leave roughness on the order of a few nanometers on waveguide sidewalls. This roughness scatters light out of the guided mode. In a well-fabricated 220 nm SOI rib waveguide, propagation loss is typically in the range of 0.5 to 2 dB/cm, depending on the etch process quality and waveguide geometry.
For a chip with a dense MZI mesh, the total waveguide length can easily reach several centimeters when all the routing is counted. Even at 1 dB/cm, several centimeters of waveguide contributes several dB to the budget. Reducing propagation loss requires either better etch process control (a foundry-level decision) or waveguide geometry choices that reduce mode confinement near the rougher sidewalls, at the cost of minimum bend radius and therefore chip area.
Absorption is less dominant in silicon at near-infrared wavelengths around 1310 nm or 1550 nm, but two-photon absorption and free-carrier absorption become relevant at higher optical powers. In an inference chip, the optical power per waveguide is generally well below the threshold where these effects dominate, so absorption is a secondary concern relative to scattering.
Insertion loss at MZI components
The heart of a photonic inference chip is the array of Mach-Zehnder interferometers. Each MZI contains two 50:50 directional couplers (or multimode interference splitters) and two phase-shifter arms. Every one of these elements contributes insertion loss.
A good directional coupler in a commercial SOI process has excess loss of roughly 0.1 to 0.3 dB. A phase-shifter arm has loss from the metal contacts that approach the waveguide for thermal heating. Depending on the heater geometry and the gap between metal and waveguide, this can add another 0.1 to 0.5 dB per arm. An MZI consisting of two couplers and two phase-shifter arms therefore contributes roughly 0.5 to 1.5 dB of insertion loss in total.
In a matrix with N MZIs in series, these losses compound. A 4x4 unitary matrix implemented as an MZI mesh requires around 6 MZI elements along the critical path. At 1 dB per MZI, that is 6 dB from the mesh alone. Scaling to larger matrices makes the loss budget the binding constraint on matrix size long before fabrication area becomes a problem.
Our primary approach to reducing per-MZI loss is a combination of optimized coupler geometry and careful phase-shifter metal placement. The coupler can be designed with a geometry that minimizes bend loss and mode mismatch at the junction. The phase-shifter heater can be placed above the waveguide with a SiO2 isolation layer rather than directly at the waveguide sidewall, reducing absorption from metal proximity at the cost of some thermal efficiency.
Detector coupling loss and responsivity
At the output of the MZI mesh, the optical signal reaches germanium photodetectors integrated on the silicon chip. The coupling between the silicon waveguide and the germanium detector involves a mode transition. Imperfect mode matching at this interface adds coupling loss, typically 0.5 to 1 dB in a well-optimized design. The detector's responsivity (amperes per watt) then sets how efficiently the remaining photocurrent is converted to a detectable electrical signal.
Germanium-on-silicon photodetectors in a standard SOI process typically achieve responsivity of 0.8 to 1.0 A/W at 1310 nm. This is not a tunable parameter; it is set by the material physics and fabrication process. What we can optimize is the waveguide-to-detector taper geometry, which determines how much of the optical mode actually enters the absorption region of the germanium.
The aggregate loss budget and its implications for precision
Adding up all of these contributions, the total optical loss from fiber input to detector output in a photonic inference chip with a non-trivial matrix size is typically in the range of 10 to 20 dB. That means the signal at the detector can be one-tenth to one-hundredth of the launched optical power. This constrains the signal-to-noise ratio of each output.
Photon shot noise scales as the square root of photocurrent. At lower photocurrents, the fractional shot noise is higher, which means each multiply-accumulate output is less precise. For inference applications, this translates to a tradeoff between matrix size, loss budget, and achievable computation precision. Larger matrices require either more launched optical power (more laser power, more energy use) or acceptance of lower precision, or both.
We are not suggesting this tradeoff eliminates the energy advantage of photonic inference. The energy saved by not heating and switching transistors is substantial, and it persists even accounting for the laser drive power needed to overcome chip losses. But the loss budget is a real constraint that determines where the architecture is viable and where it is not. Honest accounting of losses is the only way to design a system that actually works as claimed.