Why coherence matters for weight encoding
Photonic matrix multiplication works by encoding a matrix transformation in the interference pattern of light. Interference requires two or more waves to maintain a stable phase relationship relative to each other. The distance over which a light source maintains that stable phase relationship is called the coherence length. When the path length difference between interfering beams exceeds the coherence length, the interference fringe contrast drops, and your encoded weight starts losing fidelity.
For a Mach-Zehnder interferometer mesh implementing an N-by-N matrix, light travels through a series of beam splitters and phase modulators. The path length differences between the shortest and longest paths through an N-element mesh scale roughly as O(N). For small matrices, this is not a problem. For the large matrices in transformer models, it constrains your architecture choices more than most introductory discussions of photonic computing acknowledge.
The coherence length of a practical laser source
Coherence length Lc is related to the linewidth of the laser source by approximately Lc = lambda2 / delta-lambda, where lambda is the center wavelength and delta-lambda is the spectral bandwidth. For a distributed feedback (DFB) laser at 1310 nm with a linewidth around 1 MHz (a reasonable spec for a temperature-stabilized DFB used in silicon photonics applications), the coherence length works out to roughly 300 meters. For a Fabry-Perot laser with a linewidth of several GHz, the coherence length drops to centimeters.
Silicon photonic chips for neural inference typically use either an on-chip DFB laser or couple in light from an external DFB. A well-stabilized DFB source gives coherence lengths far longer than any practical chip dimension, which means coherence alone does not limit you at the single-chip scale. The issue is more subtle: it is about what happens when you try to scale to large matrix dimensions, or when you couple multiple chips to implement a matrix that does not fit on a single die.
Path length matching in large MZI meshes
Consider implementing a 64-by-64 unitary matrix using the Clements rectangular mesh decomposition. The mesh has 64*63/2 = 2016 MZI elements. Light entering from input port 0 takes the shortest path through 63 MZI stages. Light entering from input port 63 may traverse a longer path through cross-coupled routes. If the path lengths are not matched, the phase relationship between signals on different paths drifts with temperature and process variation, not just because of coherence, but because differential path length makes the effective phase shift a function of temperature through the thermo-optic coefficient of silicon (around 1.8 x 10-4 K-1).
Photonic chip designers address this through active path length balancing during layout: every routing waveguide that adds length gets a matching spiral or meander added to the opposing arm. The cost is chip area. For a 64-by-64 matrix on a silicon photonics platform with 220-nm SOI process and 2-3 dB/cm propagation loss, the total insertion loss through the mesh becomes the binding constraint before coherence length does, given a good DFB source.
Optical weight banks vs. dynamic computation
There are two distinct architectural modes for photonic neural inference. The first is dynamic: modulate the weights on every inference call, so the chip is essentially a reprogrammable matrix multiplier. The second is weight-stationary: program the weights once per model load, and hold them in the static phase settings of the MZI mesh throughout inference.
For the weight-stationary case, coherence length is relevant primarily at programming time. When you set the phase values of each MZI, you are effectively writing the weight matrix into the optical domain. Once written, inference is passive propagation through a static optical structure. The coherence constraint then mainly affects how many matrix elements you can implement in a single coherent path from a single laser source.
For the dynamic case, where you are writing new weights at inference time, you additionally need the modulation speed to keep up with token generation rates. Ring-resonator-based modulators can reach 10s of GHz but are highly temperature sensitive. MZI-based thermal modulators are more stable but are limited to MHz modulation rates. The choice between these creates a tradeoff between coherence, speed, and thermal sensitivity that we navigate differently for the weight-stationary architecture we focus on.
How this constrains matrix size in practice
The practical limit for a weight-stationary single-chip photonic matrix multiplier, given current silicon photonics process capabilities, is roughly 64 to 128 matrix dimension before insertion loss, not coherence, becomes the main fidelity problem. A 64-by-64 matrix covers projection layers of modest size. Transformer attention heads with dimension 64 or less are directly implementable. For models with wider projection matrices, you need tiling: break the large matrix into blocks, program and compute each block sequentially or across multiple chips, and accumulate the results electronically.
Tiling works well for batch inference where you have flexibility in how you schedule compute. For single-request latency use cases, the overhead of tiling and accumulation adds latency that can outweigh the energy benefit. We are not claiming the single-chip photonic processor is a drop-in replacement for GPU matrix multiply at all matrix sizes; it is architecturally strongest in the regime where the batch size is large, the projection dimension is within the chip's native matrix capacity, and you are optimizing energy per token rather than per-request latency.
What we are working on to extend the coherent volume
Two approaches are actively being pursued in the academic literature and in our own design work to push toward larger matrix dimensions. First is the use of coherent optical buses: routing light from a single high-coherence laser source to multiple chip tiles through fiber or waveguide links, maintaining phase coherence across tiles using optical phase locks. This is analogous to how phased-array antennas work in RF engineering.
Second is breaking the requirement for full coherence by moving to incoherent or partially-coherent computing architectures. Some operations, particularly those that can be decomposed into intensity-based (rather than amplitude-based) optics, do not require coherence between all input paths. The tradeoff is that incoherent architectures cannot implement arbitrary unitary transforms; they are limited to non-negative matrix operations, which covers some but not all of the neural network operations we care about.
The coherence constraint is real, it is a non-trivial architectural consideration, and anyone building photonic inference chips who does not engage with it seriously is either running very small matrices or not fully accounting for the physics. Our design choices reflect the current practical limits of single-chip coherent optical matrix processing. As laser coherence technology, chip integration density, and multi-chip optical coupling improve, the regime of practical matrix sizes will expand.